SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling
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| SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling | |||||||||||||||||||||||||||||
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SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis. SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language. In addition, the second edition features a new chapter that explanis the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools. |
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| 03-25-07 | 4 | (NA) |
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(My review is about the 2006 2nd-edition, not the older 1st edition!)
In general, I agree with the other reviews. This book is written for an audience of Verilog designers, who know the Verilog language (and its limitations) all to well. The book covers Systemverilog's new features like, enum, struct, interfaces, etc., from the perspective of "how to write better RTL-code using Systemverilog instead of Verilog.' For example, it explains the pros/cons of the (Systemverilog) "interface" construct, vs a flat group of (Verilog) module-port declarations. The discussion helps designers appreciate RTL-coding from a (slightly) higher levle of abstraction. You don't need a specific background (i.e. design-engineer) to benefit from this book; you just need a good familiarity with conventional Verilog. As others have said, this book is not suitable as a reference. The paragraphs flow well, but it's hard to lookup an arbitrary topic from the index. So far, no hardcover-book can displace the official IEEE Systemverilog LRM as the best reference. And since the book focuses on the 'design' (synthesizeable) aspect of Systemverilog, it doesn't cover non-synthesizeable language features (like classes, constrained random variables, etc.) (Review Data Last Updated: 2007-09-07 22:01:00 EST)
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| 03-25-07 | 4 | 2\2 |
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(My review is about the 2006 2nd-edition, not the older 1st edition!)
In general, I agree with the other reviews. This book is written for an audience of Verilog designers, who know the Verilog language (and its limitations) all to well. The book covers Systemverilog's new features like, enum, struct, interfaces, etc., from the perspective of "how to write better RTL-code using Systemverilog instead of Verilog.' For example, it explains the pros/cons of the (Systemverilog) "interface" construct, vs a flat group of (Verilog) module-port declarations. The discussion helps designers appreciate RTL-coding from a (slightly) higher levle of abstraction. You don't need a specific background (i.e. design-engineer) to benefit from this book; you just need a good familiarity with conventional Verilog. As others have said, this book is not suitable as a reference. The paragraphs flow well, but it's hard to lookup an arbitrary topic from the index. So far, no hardcover-book can displace the official IEEE Systemverilog LRM as the best reference. And since the book focuses on the 'design' (synthesizeable) aspect of Systemverilog, it doesn't cover non-synthesizeable language features (like classes, constrained random variables, etc.) (Review Data Last Updated: 2008-04-14 18:51:17 EST)
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| 03-24-07 | 4 | 4\4 |
| Reviewer | Permalink | ||||||||||||||||||||||||
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(My review is about the 2006 2nd-edition, not the older 1st edition!)
In general, I agree with the other reviews. This book is written for an audience of Verilog designers, who know the Verilog language (and its limitations) all to well. The book covers Systemverilog's new features like, enum, struct, interfaces, etc., from the perspective of "how to write better RTL-code using Systemverilog instead of Verilog.' For example, it explains the pros/cons of the (Systemverilog) "interface" construct, vs a flat group of (Verilog) module-port declarations. The discussion helps designers appreciate RTL-coding from a (slightly) higher levle of abstraction. You don't need a specific background (i.e. design-engineer) to benefit from this book; you just need a good familiarity with conventional Verilog. As others have said, this book is not suitable as a reference. The paragraphs flow well, but it's hard to lookup an arbitrary topic from the index. So far, no hardcover-book can displace the official IEEE Systemverilog LRM as the best reference. And since the book focuses on the 'design' (synthesizeable) aspect of Systemverilog, it doesn't cover non-synthesizeable language features (like classes, constrained random variables, etc.) (Review Data Last Updated: 2008-11-30 07:05:32 EST)
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| 03-21-07 | 3 | (NA) |
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System Verilog is the ASIC HDL of the future, and this is one of the first books specifically addressing its use for Design, as opposed to Assertions or Testbenches. As such, it is an important book. And the authors are certainly Verilog experts.
My main criticism of the book is that it's not so useful as a reference. I pull it off this shelf, flip to the back, and often find the Index lacking. It's only four pages long, which is awfully short for such a long technical textbook. (Review Data Last Updated: 2007-03-25 07:30:15 EST)
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| 10-04-04 | 4 | 7\9 |
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As an experienced hardware designer who wants to know what SV is all about, this book was great. It introduced the langauge in a natural way, explained what is synthesisable and is more readable than the LRM. You can also download the book examples from the author's website. This is the audience that this book aimed at and it hits the mark, especially as most designers can get the company to pay the high price of the book.
Downsides: there are some differences from the LRM, as this book was written before the final draft, and despite the book saying the chapter 10 complete design example simulates, it doesn't. (Review Data Last Updated: 2007-03-25 07:30:15 EST)
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